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3.17.17 SH Options

These -m options are defined for the SH implementations:

Generate code for the SH1.
Generate code for the SH2.
Generate code for the SH2e.
Generate code for the SH3.
Generate code for the SH3e.
Generate code for the SH4 without a floating-point unit.
Generate code for the SH4 with a floating-point unit that only supports single-precision arithmetic.
Generate code for the SH4 assuming the floating-point unit is in single-precision mode by default.
Generate code for the SH4.
Compile code for the processor in big endian mode.
Compile code for the processor in little endian mode.
Align doubles at 64-bit boundaries. Note that this changes the calling conventions, and thus some functions from the standard C library will not work unless you recompile it first with -mdalign.
Shorten some address references at link time, when possible; uses the linker option -relax.
Use 32-bit offsets in switch tables. The default is to use 16-bit offsets.
Enable the use of the instruction fmovd.
Comply with the calling conventions defined by Renesas.
Mark the MAC register as call-clobbered, even if -mhitachi is given.
Increase IEEE-compliance of floating-point code.
Dump instruction size and location in the assembly code.
This option is deprecated. It pads structures to multiple of 4 bytes, which is incompatible with the SH ABI.
Optimize for space instead of speed. Implied by -Os.
When generating position-independent code, emit function calls using the Global Offset Table instead of the Procedure Linkage Table.
Generate a library function call to invalidate instruction cache entries, after fixing up a trampoline. This library function call doesn't assume it can write to the whole memory address space. This is the default when the target is sh-*-linux*.